`include "definitions.sv"

module NewLabel_sysif
(
	input logic s_rstn,
	input logic sclk,

	//outer
	//output logic [23:0] data_o,
	//input  logic [7:0]	data_i,
	output logic		oe,
	input  logic [4:0]	addr,
	input  logic 		cs,
	input  logic 		wr,
	
	//inner
	output logic 		wr_valid,
	input  logic		wr_full,
	output logic 		rd_valid,
	input  logic		rd_empty,
	output logic		cs_rf,
	output logic		wr_rf,
 	output logic 		err_sysif
);

assign cs_rf = (cs & (addr[4] == 1'b0))? 1:0;
assign wr_rf = (cs_rf & wr)? 1:0;

logic fifo_hit;
assign fifo_hit = (cs & (addr == 5'b11111))? 1:0;
logic fifo_hit_rd;
assign fifo_hit_rd = (cs & (addr == 5'b11110))? 1:0;

assign wr_valid = fifo_hit & wr & (!wr_full);
assign rd_valid = fifo_hit_rd & (!wr) & (!rd_empty);

always_ff @(posedge sclk or negedge s_rstn)
begin
	if(!s_rstn)
		oe <= 1'b0;
	else if(fifo_hit_rd & (!wr) & (!rd_empty))
		oe <= 1'b1;
	else
		oe <= 1'b0;
end

//synopsys translate_off
logic [31:0]	interval_count_debug;
logic interval_start_debug;
logic cs_d_debug;
logic wr_d_debug;
always_ff @(posedge sclk)
begin
	cs_d_debug <= cs;
	wr_d_debug <= wr;
end
always_ff @(posedge sclk or negedge s_rstn)
begin
	if(!s_rstn)
		interval_start_debug <= 1'b0;
	else if(cs_d_debug == 1'b1 & cs == 1'b0 & wr_d_debug == 1'b1 & wr == 1'b0)
		interval_start_debug <= 1'b1;
	else if(interval_start_debug == 1'b1 & cs == 1'b1 & wr == 1'b0)
		interval_start_debug <= 1'b0;
end

always_ff @(posedge sclk or negedge s_rstn)
begin
	if(!s_rstn)
		interval_count_debug <= '0;
	else if(interval_start_debug)
		interval_count_debug <= interval_count_debug + 1'b1;
end
//synopsys translate_on

/*always_ff @(posedge sclk or negedge s_rstn)
begin
	if(!s_rstn)
		wr_valid <= 1'b0;
	else if(fifo_hit & wr & (!wr_full))
		wr_valid <= 1'b1;
	else
		wr_valid <= 1'b0;
end

always_ff @(posedge sclk or negedge s_rstn)
begin
	if(!s_rstn)
		rd_valid <= 1'b0;
	else if(fifo_hit & (!wr) & (!rd_empty))
		rd_valid <= 1'b1;
	else
		rd_valid <= 1'b0;
end*/

endmodule
